Balancing planarization of layers and the effect of underlying structure on the metrology signal

ABSTRACT

The present invention includes a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal.  
     One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer. The present invention also includes a system for selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure comprising a wafer fabricator, a planarizer, a layer profiler, an optical metrology device, and a selector for the selecting the design of underlying structure that yields a reflected metrology signal closest to the calibration metrology signal and where the planarized surfaces meet preset standard planarization characteristics.

[0001] This application relates to co-pending U.S. patent applicationSer. No. 09/727,530 entitled “System and Method for Real-Time LibraryGeneration of Grating Profiles” by Jakatdar, et al., filed on Nov. 28,2000, owned by the assignee of this application and incorporated hereinby reference and to co-pending U.S. patent application Ser. No.09/770,997 entitled “Caching of Intra-Layer Calculations for RapidRigorous Coupled-Wave Analyses” by Niu, et al., filed on Jan. 25, 2001,owned by the assignee of this application and incorporated herein byreference.

BACKGROUND OF INVENTION

[0002] 1. Field of Invention

[0003] This invention is in the field of manufacture of semiconductordevices. More particularly, this invention relates to a method andsystem of fabricating underlying structures to improve planarizationcharacteristics of layers while minimizing introduction of random and/orsystematic noise by the underlying structures to the metrology signal.

[0004] 2. Related Art

[0005] As feature sizes in semiconductor devices shrink,photolithographic equipment requires that layers of a wafer be very flator planar so that small feature dimensions are accurately patterned.Chemical mechanical planarization (CMP) is widely used in varioussemiconductor processing operations to planarize layers of a wafer. Thepolishing process typically uses an abrasive slurry and a combination ofmechanical and chemical actions to planarize the layer surface.

[0006] CMP performance is affected by the density of underlyingstructures in a wafer, resulting in two phenomena called “dishing” and“erosion”. FIG. 1A is an architectural diagram illustrating the“dishing” effects of the CMP process on a layer of a wafer. In a stackedwafer structure 13, the stack comprises a silicon layer or a substrate11 and a dielectric layer or layers 9, a metal seed layer 7, and aninterlayer dielectric (ILD) 5, typically silicon oxide. The metal layer3, typically copper, aluminum, or tungsten, is planarized using a CMPprocess. Since the metal layer 3 is relatively softer than the ILD plusthe chemical action of the CMP, a metal loss region 1 occurs, referredto as “dishing”.

[0007]FIG. 1B is an architectural diagram illustrating the “erosion”effects of the CMP process on a layer of a wafer. In a stacked waferstructure 20, an ILD layer 31 is fabricated above a substrate orprevious layers (not shown). Another ILD layer 25 is fabricated abovethe etch stopper layer 29. The metal layer 23 is planarized using a CMPprocess where a different polishing rate applies to the dense region 24compared to the region with small features 22. The difference in thepolishing rate is most pronounced in the middle of the small featureregion 22, resulting in a concave-profile loss region consisting of lossof ILD and metal. This phenomenon, referred to as “erosion”.

[0008] One of the solutions used to solve the local pattern densityeffect is to use fill or dummy shapes. U.S. Pat. No. 5,278,105 entitled“Semiconductor Device with Dummy Features in Active Layers” to Eden, etal., discusses the use of fill shapes for correcting problems related tolocal pattern density

[0009]FIG. 2 is an architectural diagram illustrating the use of anoptical metrology system to acquire critical dimension (CD) data offtarget periodic structures. The optical metrology system 40 consists ofa metrology beam source 41 projecting a beam 43 at the target periodicstructure 53 of a wafer 43 mounted on a metrology platform 55. Themetrology beam 43 is projected at an incidence angle θ towards thetarget periodic structure 53. The reflected beam 49 is measured by ametrology beam receiver 51. The reflected beam data 57 is transmitted toa metrology profiler system 53. The metrology profiler system 53compares the measured reflected beam data 57 against a library ofcalculated reflected beam data representing varying combinations ofcritical dimensions of the target periodic structure and resolution. Thelibrary instance best matching the measured reflected beam data 57 isselected. The profile and associated critical dimensions of the selectedlibrary instance correspond to the cross-sectional profile and criticaldimensions of the features of the target periodic structure 53. Asimilar optical metrology system 40 is described in U.S. Pat. No.5,739,909, entitled “Measurement and Control of Linewidths in PeriodicStructures Using Spectroscopic Ellipsometry”, issued to Blayo, et al.

[0010] Two spectroscopic metrology techniques are used typically tomeasure target structures in a non-destructive manner: spectroscopicreflectometry and spectroscopic ellipsometry. In reflectometry, lightintensities are measured. R=|r|² is the relation between the reflectanceR and the complex reflection coefficient r. In spectroscopicellipsometry, the component waves of the incident light, which arelinearly polarized with the electric field vibrating parallel (p or TM)or perpendicular (s or TE) to the plane of incidence, behave differentlyupon reflection. The component waves experience different amplitudeattenuations and different absolute phase shifts upon reflection; hence,the state of polarization is changed. Ellipsometry refers to themeasurement of the state of polarization before and after reflection forthe purpose of studying the properties of the reflecting boundary. Themeasurement is usually expressed as tangent (Ψ) and cosine (Δ).

[0011] In spectroscopic metrology, the reflected optical signal isconsidered ideal when the underlying structure is unpatterned, i.e.,like a unpatterned film or substrate. The presence of a pattern in theunderlying structure may introduce random and/or systematic noise to themeasured reflected optical signal. The source of random noise cannot bedetermined whereas systematic noise can possibly be determined andcharacterized. Significant random or systematic noise in the signal inturn skews the matching process of the measured reflected signal againstthe library of calculated reflected beam data, causing the match of themeasured reflected signal to a different profile and/or differentcritical dimensions.

[0012] On the other hand, the underlying structure design may notintroduce random and/or systematic noise to the measured reflectedoptical signal but the CMP characteristics of planarized layers mightexceed ranges required by the application.

[0013] Thus, there is a need for identification of an underlyingstructure that achieves improved planarization characteristics of layerswhile minimizing introduction of random and/or systematic noise to thereflected metrology signal.

SUMMARY OF INVENTION

[0014] The present invention is a method and system for identifying anunderlying structure that achieves improved planarizationcharacteristics of layers while minimizing introduction of random and/orsystematic noise to the reflected metrology signal.

[0015] One embodiment of the present invention is a method of optimizingthe design of underlying structures in a wafer with one or more designsof pads of varying sizes and varying loading factors, comparingplanarization characteristics of the underlying layers of the wafer topreset standard planarization characteristics, fabricating targetstructures in the target layer of the wafer, measuring a reflectedmetrology signal off a calibration test area to obtain a calibrationmetrology signal, the calibration test area having an unpatternedunderlying structure, and selecting the design of pads that yield areflected metrology signal closest to the calibration metrology signaland that meet preset standard planarization characteristics. Anotherembodiment is a method of designing underlying structures with one ormore designs of random shapes of varying sizes and varying loadingfactors in underlying layers of a wafer.

[0016] Still another embodiment of the present invention is a method ofoptimizing the design of underlying structures with one or more periodicstructures of varying line-to-space ratios in one or more underlyinglayers of a wafer, the periodicity of the underlying periodic structurebeing positioned at an angle relative to the direction of periodicity ofthe target periodic structure of the wafer. In one application, theangle relative to the direction of periodicity of the target periodicstructure of the wafer is ninety degrees.

[0017] The present invention also includes a system for optimizing theselection of an underlying structure design that balances planarizationand optical metrology objectives for a target structure comprising awafer fabricator, a planarizer for planarizing a surface of anunderlying layer of the wafer, a layer profiler for measuring theplanarization characteristics of planarized layers of the wafer, anoptical metrology device for processing the reflected signal from thetarget structure in the target layer of the wafer, and a selector forthe selecting the design of underlying structure that yields a reflectedmetrology signal closest to the calibration metrology signal and thatmeets preset standard planarization characteristics.

BRIEF DESCRIPTION OF DRAWINGS

[0018]FIG. 1A is an architectural diagram illustrating the “dishing”effects of the CMP process on a layer of a wafer.

[0019]FIG. 1B is an architectural diagram illustrating the “erosion”effects of the CMP process on a layer of a wafer.

[0020]FIG. 2 is an architectural diagram illustrating the use of anoptical metrology system to acquire critical dimension (CD) data offtarget periodic structures.

[0021]FIG. 3A is an architectural diagram illustrating the targetstructures, underlying structures, and interlayer dielectric, in oneembodiment of the present invention.

[0022]FIG. 3B is an architectural diagram illustrating a top view of anunderlying structure showing a calibration area and patterned areas withrandom shapes.

[0023]FIG. 3C is an architectural diagram illustrating a top view of anunderlying structure showing a calibration area and patterned areas withperiodic structures.

[0024]FIG. 4A is a graph illustrating random noise introduced inmetrology measurements due to patterns in the underlying structure.

[0025]FIG. 4B is a graph illustrating systematic noise introduced inmetrology measurements due to patterns in the underlying structure.

[0026]FIG. 4C is a graph illustrating significantly reduced randomnon-systematic noise in the metrology signal due to an underlyingstructure design that approximates the reflected metrology signal of anunpatterned underlying structure.

[0027]FIG. 5 is an architectural diagram illustrating the use of varyingsize pads for balancing the CMP effects and effects on the reflectedoptical metrology signal in one embodiment of the present invention.

[0028]FIG. 6 is an architectural diagram illustrating the use of randomshapes for balancing the CMP effects and effects on the reflectedoptical metrology signal in one embodiment of the present invention.

[0029]FIG. 7A is a cross-sectional view illustrating multi-layerunderlying structures for a dual damascene target structure in oneembodiment of the present invention.

[0030]FIG. 7B is a top-view illustrating dual layer underlyingstructures perpendicular to the direction of periodicity of the targetstructure in one embodiment of the present invention.

[0031]FIG. 8 is flow chart of operational steps of one embodiment of thepresent invention.

[0032]FIG. 9 is an architectural diagram of a system for selecting anunderlying structure design that balances planarization and opticalmetrology objectives in one embodiment of the present invention.

[0033]FIG. 10A is a graph of Tan (Ψ) versus the wavelength for aparallel underlying structure versus a perpendicular underlyingstructure in one embodiment of the present invention.

[0034]FIG. 10B is a graph of Cos (Δ) versus the wavelength for aparallel underlying structure versus a perpendicular underlyingstructure in one embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT(S)

[0035] The present invention includes a method for identifying, for agiven target structure, the design, distribution, and density of fillshapes of the underlying structures and/or the arrangement of thepatterned underlying structures that will minimize the introduction ofrandom or systematic noise to the reflected metrology signal off thetarget structure.

[0036] A summary of the process for the present invention, described indetail in FIG. 8, is provided here to facilitate the descriptions offigures that follow. Initially, the CMP and optical metrology signaldesign criteria for the target structure are set. A target structure isthe patterned structure of a layer of a wafer that is measured usingoptical metrology. A predetermined set of underlying structures,including a calibration underlying structure, is designed. Based on theCMP design criteria, a set of pads and/or random shapes of varying size,geometry, and loading factors may be designed in a mask for theunderlying structures. Alternatively, a set of periodic underlyingstructures with varying line-to-space ratios may be designed. Thepredetermined set of underlying structures and subsequent layers of thewafer are fabricated. A CMP process may be required for one or more ofthe subsequent layers of the wafer. Whenever a CMP process is involved,the CMP process characteristics of the planarized layer are measured.The target structures in the target layer of the wafer are fabricated.The reflected optical metrology signal from a calibration test area inthe target layer of the wafer is measured. Once the calibrationreflected optical metrology signal is obtained, reflected opticalmetrology signals from the other target structures with underlyingstructures varying in either loading factors or line-to-space ratios aremeasured.

[0037] In an alternative embodiment for periodic underlying structures,the reflected optical metrology signals from the target structures inthe target layer may be calculated for both the calibration test areaand the other test structures with underlying structures varying ineither loading factors or line-to-space ratios. The measured or thecalculated reflected optical metrology signals are compared to thecalibration reflected optical metrology signal and the best-fittingmeasured or calculated reflected optical metrology signal is identified.If both of the CMP and optical metrology signal design criteria are met,the underlying structure associated with the target structure identifiedas having best-fitting signal is selected as the underlying structurefor the fabrication run. Otherwise, the process is iterated startingwith designing a new set of underlying structures.

[0038]FIG. 3A is an architectural diagram illustrating the targetstructures, underlying structures, and interlayer dielectric in oneembodiment of the present invention. The first underlying structure 67is fabricated above an interlayer dielectric (ILD) or substrate 69. Thesecond underlying structure 65 is fabricated on top of the firstunderlying structure 67 with an ILD 66 in between. The target structure62 is fabricated over one or more ILD's 63. The critical dimensions andprofile of features of the target structure 62 in the target layer ismeasured with an optical metrology device, (not shown), such as the onedepicted in FIG. 2.

[0039]FIG. 3B is an architectural diagram illustrating a top view of anunderlying structure showing a calibration area and patterned areas withrandom shapes. The calibration area 72 is unpatterned whereas thepatterned areas 73 have different designs, distribution, and density offill shapes. An optical metrology device is used to measure thereflected metrology signal off the target structure above thecalibration area 72. This calibration reflected metrology signal is thebaseline for comparing the measured reflected optical metrology signalsoff the target structure above the patterned areas 73.

[0040] Similarly, FIG. 3C is an architectural diagram illustrating a topview of an underlying structure showing a calibration area and patternedareas with periodic structures. The calibration area 78 is unpatternedwhereas the patterned areas 79 have different line-to-space ratios. Anoptical metrology device is used to measure reflected metrology signaloff the target structure above the calibration area 78. This calibrationreflected metrology signal is the baseline for comparing the measuredreflected optical metrology signals off the target structure abovepatterned areas 79.

[0041]FIG. 4A is a graph illustrating random noise introduced inmetrology measurements due to patterns in the underlying structure. TheX-axis is the wavelength in nanometers while the Y-axis is cosine (Δ).The solid line graph 82 is the calculated or measured reflectedcalibration metrology signals off the target structure with anunpatterned underlying structure and shows the variation of cosine (Δ)as a function of wavelength. Use of certain fill shapes to optimize theCMP characteristics of layers of the wafer introduces random noise 81 tothe reflected metrology signal. The dotted line graph 83 of cosine (Δ)is different from the solid line graph 82 of the calculated or measuredreflected calibration metrology signals. As a result of the randomnoise, the measured reflected metrology signal for the patterned areascan have a different best-matching instance of the library of calculatedreflected optical metrology data. Thus, the profile and associatedcritical dimensions of the target structure provided by opticalmetrology would be different as a result of random noise introduced bythe underlying structure.

[0042]FIG. 4B is a graph illustrating systematic noise introduced inmetrology measurements due to patterns in the underlying structure.Similar to FIG. 4A, the X-axis is the wavelength in nanometers while theY-axis is cosine (Δ). The solid line graph 86 is the calculated ormeasured reflected calibration metrology signals of the target structurewith an unpatterned underlying structure. The dotted line graph 87 ofcosine (Δ) is different from the solid line graph 86 of the calculatedor measured reflected calibration metrology signals. As a result of thesystematic noise, the measured reflected metrology signal for thepatterned areas would have a different best-matching instance of thelibrary of calculated reflected optical metrology data. Thus, theprofile and associated critical dimensions of the target structureprovided by optical metrology would be different as a result ofsystematic noise introduced by the underlying structure.

[0043]FIG. 4C is a graph illustrating significantly reduced randomnon-systematic noise in the metrology signal due to an underlyingstructure design that approximates the reflected metrology signal of anunpatterned underlying structure. Similar to FIG. 4A, the X-axis is thewavelength in nanometers while the Y-axis is cosine (Δ). The solid linegraph 90 is the calculated or measured reflected calibration metrologysignals of the target structure with an unpatterned underlyingstructure. The underlying structures used to optimize the CMPcharacteristics of layers of the wafer resulted in significantly reducedrandom non-systematic noise 89 to the measured reflected metrologysignal off the patterned underlying areas. The measured reflectedmetrology signal off the target structures with patterned underlyingareas averages out to a graph that is close to the solid line graph 90.As a result, the best-matching instance of the library of calculatedreflected optical metrology data to the measured reflected opticalmetrology data with patterned underlying areas would provide profile andassociated critical dimensions that are acceptable for a givenfabrication run.

[0044] For a given target structure and wafer fabrication process, thepresent invention identifies the design of an underlying structure thatminimizes the introduction of random and/or systematic noise yet meetsplanarization objectives. As mentioned earlier, fill shapes, includingpads or random shapes, may be used. For fill shapes, the key factor thatintegrates the effect of design, distribution, and density is theloading factor. Loading factor is the percentage of the area covered bythe fill shapes compared to the total patterned area. The underlyingstructure may also be a periodic structure. The key factors in anunderlying structure comprising periodic structures are theline-to-space ratio and angle between the periodicity of the underlyingstructure and the periodicity of the target structure or orientation.

[0045]FIG. 5 is an architectural diagram illustrating the use of varyingsize pads for balancing the CMP effects and effects on the reflectedoptical metrology signal in one embodiment of the present invention.Fill shapes may be pads of any geometric configuration, such as squares,circles, or pentagons. FIG. 5 shows three square-shaped test underlyingareas 95, 97, and 99 of 50 micrometers (μm) with varying sizes of pads,from 20 μm to 30 μm. The loading factors for the three pads are 16%,25%, and 36% respectively. Loading factors may range from 1 to 100%. Thepresent invention optimizes the loading factor for the particular targetstructure and fabrication process.

[0046]FIG. 6 is an architectural diagram illustrating the use of randomshapes for balancing the CMP effects and effects on the reflectedoptical metrology signal in one embodiment of the present invention. Thethree square-shaped test underlying areas 111, 115, and 117 show thevarying design, distribution and, densities of random shapes 112, 116,and 118. Again, the key factor is the loading factors of the differentrandom shapes. Random shapes include geometric shape or non-geometricshapes such as “islands”.

[0047]FIG. 7A is a cross-sectional view illustrating multi-layerunderlying structures for a dual damascene target structure in oneembodiment of the present invention. The first underlying structure is aperiodic structure where the direction of periodicity is the same as thedirection of periodicity of the target structure 125. The secondunderlying structure 127 may be a simple pad, a group of random shapes,or a periodic structure whose direction of periodicity is perpendicularor substantially perpendicular to the direction of periodicity of thetarget structure 125. An incident metrology beam 121 is projected to thetarget structure 125 and the reflected metrology beam 123 is measured bya metrology device (not shown).

[0048]FIG. 7B is a top-view illustrating dual layer underlyingstructures perpendicular to the direction of periodicity of the targetstructure in one embodiment of the present invention. The secondunderlying structure 133 is a periodic structure with the direction ofperiodicity perpendicular or substantially perpendicular to thedirection of periodicity of the target structure 131. The secondunderlying structure 133 consists of lines 134 and spaces 135.Similarly, the first underlying structure 141 is also a periodicstructure with the direction of periodicity perpendicular orsubstantially perpendicular to the direction of periodicity of thetarget structure 131, consisting of lines 142 and spaces 143. The lines142 of the first underlying structure are directly under thecorresponding spaces 135 of the second underlying structure 133. Thewidth of lines 142 of the first underlying structure are sufficient tocompletely cover the width of the corresponding spaces 135 of the secondunderlying structure 133. This line-and-space arrangement of the firstunderlying structure 141 and the second underlying structure 133 reducesdiffraction of the metrology beam (not shown). The key factors thatminimize introduction of random and/or systematic noise to the reflectedmetrology signal are the line-to-space ratio of the first underlyingstructure 133 and angle between the periodicity of the underlyingstructures and the periodicity of the target structure.

[0049]FIG. 8 is flow chart of operational steps of one embodiment of thepresent invention. The CMP and optical metrology signal design criteriafor the target structure are set 200. The design criteria depend on thetarget structure fabrication process and the application. For example,if the target structure is for an application that requires a high CMPstandard, then the CMP design criteria may be stricter than anapplication that accepts a wider range of acceptable dishing and erosionin planarized layers. On the other hand, if a target structure is for anapplication where a specific profile and a very tight range of profilecritical dimensions are required, then the optical metrology signaldesign criteria may be the controlling consideration. In one embodiment,the CMP design criteria may be stated in terms of angstroms ornanometers of acceptable dishing and/or erosion. The optical metrologysignal design criteria may be expressed as percentage goodness-of-fit(GOF). GOF is the inverse of the error between the measured reflectedmetrology signal and the calibration measured reflected metrologysignal, expressed as a percentage. The best matching measured reflectedmetrology signal is one with the least error compared to the calibrationreflected metrology signal. Several optimization procedures areavailable to minimize the error, such as simulated annealing, describedin “Numerical Recipes,” section 10.9, Press, Flannery, Teulkolsky &Vetterling, Cambridge University Press, 1986; which is incorporated byreference. The error metric that produces appropriate results is thesum-squared-difference-log error, where the optimization procedureminimizes the error metric between the measured reflected metrologysignal and the calibration reflected metrology signal.

[0050] A predetermined set of underlying structures, including acalibration underlying structure, is designed 210. Based on the designcriteria, a set of pads and/or random shapes of varying size, geometry,and loading factors may be designed in a mask. Alternatively, a set ofperiodic underlying structures with varying line-to-space ratios may bedesigned. In one embodiment, the underlying structures may comprise ofcircular pads with loading factors from about fifty to about ninety fivepercent (50-95%). In an alternative embodiment, the underlying structuremay comprise of two layers where the top layer is a periodic structurewith line-to-space ratio of 0.10 to 0.60 and a bottom layer withline-to-space ratio of 0.10 to 0.60 with the bottom layer line centeredbelow the corresponding top layer space. In still another embodiment fora periodic underlying structure, the angle between the periodicity ofthe underlying structures and the periodicity of the target structure isninety degrees.

[0051] The predetermined set of underlying structures and subsequentlayers of the wafer are fabricated 220. A CMP process may be requiredfor one or more of the subsequent layers of the wafer. Whenever a CMPprocess is involved, the CMP process characteristics of the planarizedlayer are measured 230. In one embodiment, the extent of dishing and/orerosion in angstroms is measured. Other measures such as long-scanmeasurement of dishing, erosion, step height, and planarity may be used.In still other embodiments, micro-scratches, and/or three-dimensionalmapping of flatness may be measured. Examples of devices capable of theaforementioned measurement are available from Digital Instruments, VeecoMetrology Group, KLA-Tencor, and other atomic force profilermanufacturers. The target structures in the target layer of the waferare fabricated 250.

[0052] The reflected optical metrology signal from a calibration testarea in the target layer of the wafer is measured 260. A calibrationtest area in the target layer of the wafer is one whose underlyingstructure is an unpatterned layer. Once the calibration reflectedoptical metrology signal is obtained, reflected optical metrologysignals from the other target structures with underlying structuresvarying in either loading factors or line-to-space ratios are measured270.

[0053] In an alternative embodiment for periodic underlying structures,the reflected optical metrology signals from the target structures inthe target layer may be calculated 295 for both the calibration testarea and the other test structures with underlying structures varying ineither loading factors or line-to-space ratios. Calculations ofreflected optical metrology signals may be done by a number oftechniques. One calculation technique is the so-called rigorouscoupled-wave analysis (RCWA). The details of an application of RCWA incalculating the reflected optical metrology signals is contained inco-pending U.S. patent application Ser. No. 09/770,997 entitled “Cachingof Intra-Layer Calculations for Rapid Rigorous Coupled-Wave Analyses” byNiu, et al., filed on Jan. 25, 2001, owned by the assignee of thisapplication, the entire content of which is incorporated herein byreference.

[0054] The measured or the calculated reflected optical metrologysignals are compared to the calibration reflected optical metrologysignal and the best-fitting measured or calculated reflected opticalmetrology signal is identified 280. In one embodiment, the best fittingsignal is identified by GOF and the best fitting signal in this case isthe underlying structure with the highest GOF. For example, the highestGOF in a wafer may be 99.5%. The associated CMP characteristics of thetarget structure with the highest GOF are compared to the CMP designcriteria. Similarly, the highest GOF is compared to the opticalmetrology signal design criteria. If both of the CMP and opticalmetrology signal design criteria are met 290, the underlying structureassociated with target structure with the highest GOF is selected as theunderlying structure for the fabrication run. Otherwise, the processproceeds to step 210 to iterate the steps starting with the designing anew set of underlying structures.

[0055]FIG. 9 is an architectural diagram of a system for selecting anunderlying structure design that balances planarization and opticalmetrology objectives in one embodiment of the present invention. Anunderlying structure designer 300 is used to create designs ofunderlying structures for a given target structure. The design includesa calibration underlying structure and other underlying structures withvarying loading factors and/or line-to-space ratios. The underlyingstructure design is used in a wafer fabricator 320 to fabricate theunderlying structures and layer(s). The wafer is planarized by theplanarizer 330 and the planarized surface is measured by a layerprofiler 340, sending the planarization characteristics to the designselector 350. An example of the layer profiler is the atomic forceprofiler mentioned previously. After measurement by the layer profiler340 of the planarization characteristics, target structures of thetarget layer of the wafer are fabricated by the wafer fabricator 320.Once the target structures are completed, the calibration test area, anarea in the target layer that has an unpatterned underlying layer, ismeasured using an optical metrology device 360. Other target structuresof the target layer are also measured by the optical metrology device360, with both measurements sent to the design selector 350.

[0056] Alternatively, specifications of underlying structure designsfrom the wafer fabricator 320 may be input into a reflected metrologysignal estimator 370 to calculate the reflected signal from thecalibration test area and from each of the target structures with eithervarying loading factors in the case of pads and random shapes or varyingline-to-space ratios in the case of periodic structures.

[0057] Still referring to FIG. 9, the design selector 350 uses eitherthe calculated or measured reflected metrology signal from thecalibration test area and selects the calculated or measured reflectedmetrology signal from the other target structures that has the highestGOF compared to the calculated or measured reflected metrology signalfrom the calibration test area. Planarization and metrologycharacteristics of the selected target structure are compared to theplanarization and optical metrology design criteria. If theplanarization and optical metrology design criteria are met, then theselected target structure is identified as having an acceptable balanceof planarization and optical metrology characteristics. In other words,the underlying structure design improves planarization characteristicsof wafer layers while minimizing the introduction, by the underlyingstructures, of random and/or systematic noise to the reflected opticalmetrology signal. If the planarization and optical metrology designcriteria are not met, then this condition is transmitted to theunderlying structure designer 300 such that a new iteration of theprocess is started for a different design. In addition, an iteration ofthe process may be done when there is a change in the fabricationprocess and/or change of fabrication materials.

[0058]FIG. 10A is a graph of Tan (Ψ) versus the wavelength for aparallel underlying structure versus a perpendicular underlyingstructure in one embodiment of the present invention. The Tan (Ψ) versusthe wavelength graph 151 of the reflected metrology signal for anunderlying structure whose periodicity is perpendicular to theperiodicity of the target structure shows a significant number of spikeswith big amplitudes. On the contrary, the Tan (Ψ) versus the wavelengthgraph 153 of the reflected metrology signal for an underlying structurewhose periodicity is parallel to the periodicity of the target structureshows a small number of spikes with small amplitudes. The two graphs 151and 153 were obtained by using a constant line-to-space ratio for theunderlying structures. Similarly, FIG. 10B is a graph of Cos (Δ) versusthe wavelength for a parallel underlying structure versus aperpendicular underlying structure in one embodiment of the presentinvention. The Cos (Δ) versus the wavelength graph 155 of the reflectedmetrology signal for an underlying structure whose periodicity isperpendicular to the periodicity of the target structure shows asignificant number of spikes with big amplitudes. On the contrary, theCos (Δ) versus the wavelength graph 157 of the reflected metrologysignal for an underlying structure whose periodicity is parallel to theperiodicity of the target structure shows a small number of spikes withsmall amplitudes. The two graphs 155 and 157 were obtained by using aconstant line-to-space ratio for the underlying structure. From anoptical metrology point-of-view, graphs with more spikes and greateramplitudes are preferred as there is more differentiation of one targetstructure profile versus another target structure profile.

[0059] Foregoing described embodiments of the invention are provided asillustrations and descriptions. They are not intended to limit theinvention to precise form described. In particular, it is contemplatedthat functional implementation of invention described herein may beimplemented equivalently in hardware, software, firmware, and/or otheravailable functional components or building blocks.

[0060] Other variations and embodiments are possible in light of aboveteachings, and it is thus intended that the scope of invention not belimited by this Detailed Description, but rather by claims following.

What is claimed is:
 1. A method of designing underlying structures in awafer that balances planarization and optical metrology characteristics,the method comprising: fabricating underlying structures including oneor more pads and one or more spaces, the one or more pads varying insize and/or shape; comparing planarization characteristics of planarizedlayer or layers of the wafer to preset standard planarizationcharacteristics; fabricating target structures in the target layer ofthe wafer; measuring a reflected metrology signal off a calibration testarea of the target layer of the wafer to obtain a calibration metrologysignal, the calibration test area having an unpatterned underlyingstructure; and selecting the design of pads of the underlying structurethat yields a reflected metrology signal off the target structure thatis closest to the calibration metrology signal and that meet preset thestandard planarization characteristics.
 2. A method of fabricatingunderlying structures in a wafer that balances planarization and opticalmetrology characteristics, the method comprising: fabricating one ormore underlying structures with a predetermined design in a wafer, thepredetermined design selected to meet planarization objectives andoptical metrology objectives, the optical metrology objectivescomprising quality of reflected metrology signal, planarizing a surfaceof a layer of the wafer, the planarized surface of the layer of thewafer having planarization characteristics, and fabricating a targetperiodic structure in the wafer; wherein the planarizationcharacteristics of the planarized surface of the layer of the wafer meetthe planarization objectives and wherein quality of a reflectedmetrology signal off the target periodic structure meet the opticalmetrology objectives.
 3. The method of claim 2 wherein the planarizationcharacteristics of the planarized surface of the wafer comprisemeasurements of extent of erosion and dishing of materials of theplanarized layer of the wafer.
 4. The method of claim 2 wherein the oneor more underlying structures include shapes and spaces, the one or moreunderlying structures having a loading factor, the loading factor beingthe ratio of area occupied by shapes to the area occupied by both theshapes and spaces.
 5. The method of claim 4 wherein the shapes includepads with geometric shapes.
 6. The method of claim 4 wherein the shapesinclude pads with irregular shapes.
 7. The method of claim 4 wherein theshapes include geometric shapes positioned in a random manner.
 8. Themethod of claim 2 wherein the one or more underlying structures in thewafer is an underlying periodic structure, the periodicity of theunderlying periodic structure being positioned at an angle relative tothe direction of periodicity of the target periodic structure of thewafer.
 9. A method of fabricating underlying structures in a wafer thatbalances planarization and optical metrology characteristics, the methodcomprising: fabricating one or more underlying structures with apredetermined design in a wafer, the predetermined design selected tomeet planarization objectives and optical metrology objectives, theoptical metrology objectives comprising quality of reflected metrologysignal, planarizing a surface of a layer of the wafer, the planarizedsurface of the layer of the wafer having planarization characteristics,and fabricating a target periodic structure in the wafer; wherein theplanarization characteristics of the planarized surface of the layer ofthe wafer meet the planarization objectives and wherein quality of areflected metrology signal off the target periodic structure meet theoptical metrology objectives; and wherein the one or more underlyingstructures in the wafer are underlying periodic structures, theperiodicity of the underlying periodic structures positionedperpendicular to the direction of periodicity of the target periodicstructure of the wafer.
 10. A method of fabricating underlyingstructures in a wafer that balances planarization and optical metrologycharacteristics, the method comprising: fabricating one or moreunderlying structures with a predetermined design in a wafer, thepredetermined design selected to meet planarization objectives andoptical metrology objectives, the optical metrology objectivescomprising quality of reflected metrology signal, planarizing a surfaceof a layer of the wafer, the planarized surface of the layer of thewafer having planarization characteristics, and fabricating a targetperiodic structure in the wafer; wherein the planarizationcharacteristics of the planarized surface of the layer of the wafer meetthe planarization objectives and wherein quality of a reflectedmetrology signal off the target periodic structure meet the opticalmetrology objectives; and wherein the one or more underlying structuresin the wafer comprises a first layer of underlying periodic structureand a second layer of underlying periodic structure, the periodicity ofthe first layer of underlying periodic structure and the second layer ofunderlying periodic structure being positioned perpendicular to thedirection of periodicity of the target periodic structure of the wafer.11. The method of claim 10 wherein the second layer of underlyingperiodic structure includes lines and spaces, the spaces being opticallytransparent to metrology signals.
 12. The method of claim 11 wherein thesecond layer of the underlying periodic structure comprises lines andspaces and the line-to-space ratio ranges from 0.10 to 0.60.
 13. Themethod of claim 11 wherein the number of spaces of the second layer ofthe underlying structure is 2, 4, or
 6. 14. The method of claim 10wherein the target periodic structure is fabricated using a singledamascene lithographic and etch process.
 15. The method of claim 10wherein the target periodic structure is fabricated using a dualdamascene lithographic and etch process.
 16. A method of designingunderlying structures in a wafer that balances planarization and opticalmetrology characteristics, the method comprising: fabricating underlyingstructures including one or more random shapes and one or more spaces,the one or more random shapes varying in size and/or shape; comparingplanarization characteristics of the underlying layers of the wafer topreset standard planarization characteristics; fabricating targetstructures in the target layer of the wafer; measuring a reflectedmetrology signal off a calibration test area of the target layer of thewafer to obtain a calibration metrology signal, the calibration testarea having an unpatterned underlying structure; and selecting anunderlying structure of the underlying structures of one or more randomshapes that yields a reflected metrology signal off the target structurethat is closest to the calibration metrology signal, the selectedunderlying structure having planarized layers that meet the presetstandard planarization characteristics.
 17. A method of designingunderlying structures in a wafer that balances planarization and opticalmetrology characteristics, the method comprising: fabricating underlyingstructures with one or more periodic structures, the one or moreperiodic structures having one or more lines and one or more spaces inone or more underlying layers of a wafer; comparing planarizationcharacteristics of one or more planarized layers of the wafer to presetstandard planarization characteristics; fabricating target structures inthe target layer of the wafer; measuring a reflected metrology signaloff a calibration test area of the target layer of the wafer to obtain acalibration metrology signal, the calibration test area having anunpatterned underlying structure; and selecting an underlying structureof the underlying structures with one or more periodic structures thatyields a reflected metrology signal off the target structure that isclosest to the calibration metrology signal, the selected underlyingstructure having one or more planarized layers that meet the presetstandard planarization characteristics.
 18. The method of designingunderlying structures of claim 17 wherein the underlying structures withone or more periodic structures comprise: a first periodic underlyingstructure in a first underlying layer with a predetermined line-to-spaceratio, the line-to-space ratio being the ratio of area occupied by thelines to the area occupied by the spaces; and a second periodicunderlying structure in a second underlying layer, the second periodicunderlying structure having lines covering the spaces of the firstperiodic underlying structure.
 19. The method of designing underlyingstructures of claim 18 wherein the number of lines of the firstunderlying structure is 2, 4, or
 6. 20. A method of selecting anunderlying structure design that balances planarization and opticalmetrology objectives for a target structure, the method comprising:fabricating underlying structures in underlying layers of a wafer, theunderlying structures designed to balance planarization and opticalmetrology objectives; measuring planarization characteristics of theunderlying layers of the wafer; fabricating a target structure in atarget layer of the wafer; measuring optical metrology characteristicsof the target structure; and comparing the planarization characteristicsof the underlying layers to the planarization objectives and the opticalmetrology characteristics of the target structure to the opticalmetrology objectives.
 21. The underlying structure design optimizationmethod of claim 20 wherein measuring optical metrology characteristicsof the target structure further comprises: calculating a reflectedmetrology signal from the target structure assuming the underlyinglayers are unpatterned; measuring an actual reflected metrology signalfrom the target structure; and comparing the calculated reflectedmetrology signal to the actual reflected metrology signal from thetarget structure.
 22. The underlying structure design optimizationmethod of claim 20 wherein the planarization objectives comprise limitson dimensions of dishing and erosion in the underlying planarizedlayers.
 23. The underlying structure design optimization method of claim20 wherein the optical metrology objectives comprises meeting apredetermined goodness of fit, the goodness of fit being the inverse ofthe error metric between the calculated reflected metrology signal tothe actual reflected metrology signal from the target structure.
 24. Theunderlying structure design optimization method of claim 20 wherein theunderlying structures in the underlying layers of the wafer includepads, random shapes, or periodic structures.
 25. A system for selectingan underlying structure design that balances planarization and opticalmetrology objectives for a target structure, the system comprising: awafer fabricator, for fabricating underlying structures in underlyinglayers of a wafer, the underlying structures designed to balanceplanarization and optical metrology objectives, and for fabricatingtarget structures in a target layer of the wafer; a planarizer forplanarizing a surface of one or more layers of the wafer, the planarizedsurface of the layer of the wafer having planarization characteristics;a layer profiler for measuring the planarization characteristics ofplanarized surfaces of the wafer; an optical metrology device forprojecting a signal on the target structure in the target layer of thewafer and for processing the reflected signal from the target structurein the target layer of the wafer; and a design selector for theselecting the design of an underlying structure that yields a reflectedmetrology signal off the target structure that is closest to thecalibration metrology signal and that meets planarization objectives;wherein the wafer fabricator fabricating underlying structures inunderlying layers of the wafer, the planarizer planarizing the surfaceof one or more underlying layers of the wafer, the layer profilermeasuring the planarization characteristics of planarized surfaces ofthe wafer, the wafer fabricator fabricating the target structures in thetarget layer of the wafer, the optical metrology device projectingmetrology signals on the target structures in the target layer of thewafer and processing the reflected metrology signals from the targetstructures, the design selector compares the reflected metrology signaloff the target structure to a calibration metrology signal, thecalibration metrology signal being the reflected metrology signal off atarget structure with an unpatterned underlying layer, and selects adesign of the underlying structure that yields a reflected metrologysignal that is closest to the calibration metrology signal and where theplanarized surfaces of the wafer associated with the selected design ofthe underlying structure meet the planarization objectives.
 26. Thesystem of claim 25 wherein the underlying structures comprises one ormore pads and one or more spaces, the one or more pads varying in sizeand/or shape.
 27. The system of claim 25 wherein the underlyingstructures comprises one or more random shapes and one or more spaces,the one or more random shapes varying in size and/or shape.
 28. Thesystem of claim 25 wherein the underlying structures comprises one ormore periodic structures, the one or more periodic structures having onemore lines and one or more spaces in one or more underlying layers ofthe wafer.
 29. The system of claim 25 wherein the underlying structurescomprise: a first periodic underlying structure in a first underlyinglayer with a predetermined line-to-space ratio, the line-to-space ratiobeing the ratio of area occupied by the lines to the area occupied bythe spaces; and a second periodic underlying structure in a secondunderlying layer, the second periodic underlying structure having linescovering the spaces of the first periodic underlying structure.
 30. Thesystem of claim 25 wherein the selector is a microcontroller programmedto compare the reflected metrology signal off the target structure to acalibration metrology signal, the calibration metrology signal being thereflected metrology signal off a target structure with an unpatternedunderlying layer; to select a design of the underlying structure thatyields a reflected metrology signal that is closest to the calibrationmetrology signal; and to ensure the design of the underlying structuremeets preset standard planarization characteristics.
 31. Acomputer-readable storage medium containing computer executable code toselect an underlying structure design that balances planarization andoptical metrology objectives for a target structure by instructing acomputer to operate as follows: comparing planarization characteristicsof underlying layers of the wafer to preset standard planarizationcharacteristics; measuring a reflected metrology signal off acalibration test area of a target layer of the wafer to obtain acalibration metrology signal, the calibration test area having anunpatterned underlying structure; and selecting a design of anunderlying structure, the underlying structure having a target structurethat yields a reflected metrology signal off the target structureclosest to the calibration metrology signal and having the planarizationcharacteristics of planarized underlying layers meet the preset standardplanarization characteristics.
 32. A method of providing a service forselecting the selecting an underlying structure design that balancesplanarization and optical metrology objectives for a target structure,the method comprising: contracting by a client and a vendor, for theclient to remunerate the vendor for the use of systems, processes, andprocedures to select an underlying structure design that balancesplanarization and optical metrology objectives for a target structure;and providing by the vendor to the client access to systems, processes,and procedures to compare planarization characteristics of underlyinglayers of the wafer to preset planarization objectives, to measure areflected metrology signal off a calibration test area of a target layerof the wafer to obtain a calibration metrology signal, the calibrationtest area having an unpatterned underlying structure, and to select thedesign of underlying structure that yields a reflected metrology signaloff the target structure that is closest to the calibration metrologysignal and where associated planarization characteristics of theunderlying layers of the wafer meet the preset planarization objectives.